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ICS9UMS9610 idt tm /icst m pc main clock 1336?06/01/09 pc main clock 1 datasheet recommended application: features/benefits: poulsbo based ultra-mobile pc (umpc) - ck610 ? supports dothan ulv cpus with 100 to 200 mhz cpu outputs dedicated test/sel and test/mode pins saves isolation resistors on pins cpu stop# input for power manangment fully integrated vreg integrated series resistors on differential outputs 1.5v vdd io, 1.5v vdd core, 3.3v vdd supply pin for ref pin configuration output features: 3 - cpu low power differential push-pull pairss 3 - src low power differential push-pull pairs 1 - lcd100 sscd low power differential push-pull pair 1 - dot96 low power differential push-pull pair 1 - ref, 14.31818mhz, 3.3v se output cput0_lpr cpuc0_lpr vddio_1.5 gndcpu cput1_lpr cpuc1_lpr vddcore_1.5 vddio_1.5 gndcpu cput2_lpr cpuc2_lpr fsb_l_1.5 48 47 46 45 44 43 42 41 40 39 38 37 cpu_stop#_3.3 1 36 *cr#2_1.5 clkpwrgd#/pd_3.3 2 35 srct2_lpr x2 3 34 srcc2_lpr x1 4 33 gndsrc vddref_3.3 5 32 srct1_lpr ref_3.3_2x 6 31 srcc1_lpr gndref 7 30 vddio_1.5 vddcore_1.5 8 29 vddcore_1.5 fsc_l_1.5 9 28 *cr#1_1.5 test_mode_1.5 10 27 srct0_lpr test_sel_1.5 11 26 srcc0_lpr sclk_3.3 12 25 gndsrc 13 14 15 16 17 18 19 20 21 22 23 24 sdata_3.3 vddcore_1.5 vddio_1.5 dot96c_lpr dot96t_lpr gnddot gndlcd lcd100c_lpr lcd100t_lpr vddio_1.5 vddcore_1.5 *cr#0_1.5 * indicates inputs with internal pull up of ~10kohm to 1.5v 48-pin mlf, 6x6 mm, 0.4mm pitch 9ums9610
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 2 pin description pin # pin name type description logic level (v) input level tolerance (v) 1 cpu_stop#_3.3 in this active-low input stops all cpu clo cks that are set to be stoppable. 3.3 3.3 2 clkpwrgd#/pd_3.3 in this level sensitive strobe determines when latch inputs are valid and are ready to be sampled. when high, this asynchronous input places the device into the power down state. 3.3 3.3 3 x2 out crystal output, nominally 14.318mhz n/a n/a 4 x1 in crystal input, nominally 14.318mhz. 1.5 1.5 5 vddref_3.3 pwr power pin for the xtal and ref clocks, nominal 3.3v 3.3 3.3 6 ref_3.3_2x out 3.3v 14.318 mhz reference clock. default 2 load drive strength 3.3 n/a 7 gndref gnd ground pin for the ref outputs. 0 n/a 8 vddcore_1.5 pwr 1.5v power for the pll core 1.5 1.5 9 fsc_l_1.5 in low threshold input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 1.5v max input voltage. 1.5 1.5 10 test_mode_1.5 in test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. max input voltage is 1.5v. 1.5 3.3 11 test_sel_1.5 in test_sel: latched input to select test mode. max input voltage is 1.5v 1 = all outputs are tri-stated for test 0 = all outputs behave normally. 1.5 3.3 12 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant. 3.3 3.3 13 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 3.3 3.3 14 vddcore_1.5 pwr 1.5v power for the pll core 1.5 1.5 15 vddio_1.5 pwr power supply for low power differential outputs, nominal 1.5v. 1.5 1.5 16 dot96c_lpr out complement clock of low power differential pair for 96.00mhz dot clock. no 50ohm resistor to gnd needed. no rs needed. 0.8 n/a 17 dot96t_lpr out true clock of low power differential pair for 96.00mhz dot clock. no 50ohm resistor to gnd needed. no rs needed. 0.8 n/a 18 gnddot gnd ground pin for dot clock output 0 n/a 19 gndlcd gnd ground pin for lcd clock output 0 n/a 20 lcd100c_lpr out complement clock of low power differential pair for lcd100 ss clock. no 50ohm resistor to gnd needed. no rs needed. 0.8 n/a 21 lcd100t_lpr out true clock of low power differential pair for lcd100 ss clock. no 50ohm resistor to gnd needed. no rs needed. 0.8 n/a 22 vddio_1.5 pwr power supply for low power differential outputs, nominal 1.5v. 1.5 1.5 23 vddcore_1.5 pwr 1.5v power for the pll core 1.5 1.5 24 *cr#0_1.5 in 1.5v clock request for src0, 0 = enable, 1 = disable 1.5 1.5
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 3 pin description (continued) pin # pin name type description logic level (v) input level tolerance (v) 25 gndsrc gnd ground pin for the src outputs 0 n/a 26 srcc0_lpr out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 0.8 n/a 27 srct0_lpr out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 0.8 n/a 28 *cr#1_1.5 in 1.5v clock request for src1, 0 = enable, 1 = disable 1.5 1.5 29 vddcore_1.5 pwr 1.5v power for the pll core 1.5 1.5 30 vddio_1.5 pwr power supply for low power differential outputs, nominal 1.5v. 1.5 1.5 31 srcc1_lpr out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 0.8 n/a 32 srct1_lpr out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 0.8 n/a 33 gndsrc gnd ground pin for the src outputs 0 n/a 34 srcc2_lpr out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 0.8 n/a 35 srct2_lpr out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 0.8 n/a 36 *cr#2_1.5 in 1.5v clock request for src2, 0 = enable, 1 = disable 1.5 1.5 37 fsb_l_1.5 in low threshold input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 1.5v max input voltage. 1.5 1.5 38 cpuc2_lpr out complementary clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 0.8 n/a 39 cput2_lpr out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 0.8 n/a 40 gndcpu gnd ground pin for the cpu outputs 0 n/a 41 vddio_1.5 pwr power supply for low power differential outputs, nominal 1.5v. 1.5 1.5 42 vddcore_1.5 pwr 1.5v power for the pll core 1.5 1.5 43 cpuc1_lpr out complementary clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 0.8 n/a 44 cput1_lpr out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 0.8 n/a 45 gndcpu gnd ground pin for the cpu outputs 0 n/a 46 vddio_1.5 pwr power supply for low power differential outputs, nominal 1.5v. 1.5 1.5 47 cpuc0_lpr out complementary clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 0.8 n/a 48 cput0_lpr out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 0.8 n/a
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 4 funtional block diagram power groups vdd gnd 41, 46 low power outputs 42 vddcore_1.5v 30 low power outputs 29 vddcore_1.5v 22 low power outputs 23 vddcore_1.5v 15 low power outputs 14 vddcore_1.5v 57 xtal, ref srcclk lcdclk dot 96mhz 18 pin number description 19 25, 33 cpuclk 40, 45 cpu(2:0) src(2:0) lcd ss-pll fslb ckpwrgd/pd# cpu_stop# cr(2:0)# testsel testmode control logic 96m non-ss pll lcd100_ssc cpu, src ss-pll ref osc x1 x2 dot96mhz fslc smbdat smbclk
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 5 absolute maximum ratings parameter symbol conditions min max units notes 3.3v supply voltage vddxxx_3.3 supply voltage 3.9 v 1,2 1.5v supply voltage vddxxx_1.5 supply voltage 2.1 v 1,2 3.3_input high voltage v ih3.3 3.3v inputs vdd_3.3+ 0.3v v 1,2,3 1.5_input high voltage v ih1.5 1.5v inputs vdd_1.5+ 0.3v v 1,2,3 minimum input voltage v il any input gnd - 0.5 v 1 storage temperature ts - -65 150 c1,2 input esd protection esd prot human body model 2000 v 1,2 notes: 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied, nor guaranteed. 3 maximum input voltage is not to exceed maximum vdd electrical characteristics - input/supply/common output parameters parameter symbol conditions min max units notes ambient operating temp tambient no airflow 0 85 c 1 3.3v supply voltage vdd xxx_3.3 3.3v +/- 5% 3.135 3.465 v 1 1.5v supply voltage vdd xxx_1.5 1.5v +/- 5% 1.425 1.575 v 1 3.3v input high voltage v ihse3.3 single-ended inputs 2 v ddxx_3.3 + 0.3 v1 3.3v input low voltage v ilse3.3 single-ended inputs v ss - 0.3 0.8 v 1 1.5v input high voltage v ihse1.5 single-ended inputs 1.2 v ddxxx_1.5 + 0.3 v1 1.5v input low voltage v ilse1.5 single-ended inputs v ss - 0.3 0.3 v 1 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input leakage current i inres inputs with pull or pull down resistors v in = v dd , v in = gnd -200 200 ua 1 output high voltage v ohs e single-ended output, i oh = -1ma 2.4 v 1 output low voltage v ols e single-ended output, i ol = 1 ma 0.4 v 1 low threshold input- high voltage v ih_fs 1.5 v +/-5% 0.7 1.5 v 1 low threshold input- low voltage v il_fs 1.5 v +/-5% v ss - 0.3 0.35 v 1 i dd_3.3 3.3v supply 10 ma 1 i dd_default1.5 1.5v core supply, lcdpll off 45 ma 1 i dd_lcden1.5 1.5v core supply, lcdpll enabled 55 ma 1 i dd_io1.5 1.5v supply, differential io current, all outputs enabled 15 ma 1 i dd_pd3.3 3.3v supply, power down mode 0.5 ma 1 i dd_pd1.5core 1.5v core supply, power down mode 0.5 ma 1 i dd_pd1.5io 1.5v io supply, power down mode 0.1 ma 1 input frequency f i v dd = 3.3 v 15 mhz 2 pin inductance l pin 7nh1 c in logic inputs 1.5 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 3 5 pf 1 spread spectrum modulation frequency f ssmod triangular modulation 30 33 khz 1 operating supply current power down current input capacitance
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 6 ac electrical characteristics - input/common parameters parameter symbol conditions min max units notes clk stabiliz ation t stab from vdd power-up or de- assertion of pd# to 1st clock 1.8 ms 1 tdrive_pd# t drpd differential output enable after pd# de-assertion 300 us 1 tdrive_cpu t drsrc cpu output enable after cpu_stop# de-assertion 26cycles1 tfall_pd# t fall 5ns1 trise_pd# t rise 5ns1 fall/rise time of pd# and cpu_stop# inputs ac electrical characteristics - low power differential outputs parameter symbol conditions min max units notes rising edge slew rate t slr differential measurement 0.6 4 v/ns 1,2 falling edge slew rate t flr differential measurement 0.6 4 v/ns 1,2 rise/fall time variation t slvar single-ended measurement 125 ps 1 maximum output voltage v high includes overshoot 1150 mv 1 minimum output voltage v low includes undershoot -300 mv 1 differential voltage swing v swing differential measurement 300 mv 1 crossing point voltage v xabs single-ended measurement 300 550 mv 1,3,4 crossing point variation v xabsvar single-ended measurement 140 mv 1,3,5 duty cycle d cyc differential measurement 45 55 % 1 cpu jitter - cycle to cycle cpuj c2c differential measurement 85 ps 1 src jitter - cycle to cycle srcj c2c differential measurement 125 ps 1 dot jitter - cycle to cycle dotj c2c differential measurement 250 ps 1 lcd jitter - cycle to cycle lcdj c2c differential measurement 85 ps 1 cpu[2:0] skew cpu skew10 differential measurement 100 ps 1 src[2:0] skew src skew differential measurement 250 ps 1 electrical characteristics - ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 clock period t p eriod 14.318mhz output nominal 69.8203 69.8622 ns 2 absolute min/max period t abs 14.318mhz output nominal 69.8203 70.86224 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -33 -33 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 1000 ps 1
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 7 electrical characteristics - smbus interface parameter symbol conditions min max units notes smbus voltage v dd 2.7 3.6 v 1 low-level output voltage v ols m b @ i pullup 0.4 v 1 current sinking at v olsmb = 0.4 v i pullup smb data pin 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 maximum smbus operating frequency f smbus block mode 100 khz 1 notes on electrical characteristics: 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around differential zero 3 vxabs is defined as the voltage where clk = clk# 4 only applies to the differential rising edge (clk rising and clk# falling) 6 all long term accuracy and clock period specifications are guaranteed assuming that ref is at 14.31818mhz 7 operation under these conditions is neither implied, nor guaranteed. 9 see pci clock-to-clock delay figure 8 maximum input voltage is not to exceed maximum vdd 5 defined as the total variation of all crossing voltages of clk rising and clk# falling. matching applies to rising edge rate of clk and falling edge of clk#. it is measured using a +/-75mv window centered on the average cross point where clk meets clk#. the average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. clock periods differential outputs with spread spectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term average long-term average period long-term average short-term average period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum src 100 9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.17630 ns 1,2 cpu 100 9.91400 9.99900 9.99900 10.00000 10.00100 10.05130 10.13630 ns 1,2 cpu 133 7.41425 7.49925 7.49925 7.50000 7.50075 7.53845 7.62345 ns 1,2 clock periods differential outputs with spread spectrum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term average long-term average period long-term average short-term average period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum src 100 9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2 cpu 100 9.91400 9.99900 10.00000 10.00100 10.13630 ns 1,2 cpu 133 7.41425 7.49925 7.50000 7.50075 7.62345 ns 1,2 dot 96 10.16560 10.41560 10.41670 10.41770 10.66770 ns 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz measurement window units notes symbol definition signal name signal name notes symbol definition measurement window units
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 8 table 1: cpu frequency select table fs l c 1 fs l b 1 cpu mhz src mhz dot mhz lcd100 mhz ref mhz 0 0 133.33 0 1 166.67 1 0 100.00 1 1 200.00 1. fs l c is a low-threshold input.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 100.00 96.00 100.00 14.318 table 2: lcd spread select table (pin 20/21) b1b5 b1b4 b1b3 spread % comment 0 0 0 -0.5% lcd100 0 0 1 -1% lcd100 0 1 0 -2% lcd100 0 1 1 -2.5% lcd100 1 0 0 +/- 0.25 % lcd100 1 0 1 +/-0.5% lcd100 1 1 0 +/-1% lcd100 1 1 1 +/-1.25% lcd100
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 9 general i 2 c serial interface information for the ICS9UMS9610 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 10 byte 0 pll & divider enable register bit ( s ) pin # name descri p tion t yp e 0 1 default 7 - pll1 enable this bit controls whether the pll driving the cpu and src clocks is enabled or not. rw 0 = disabled 1 = enabled 1 6 - pll2 enable this bit controls whether the pll driving the dot and clock is enabled or not. rw 0 = disabled 1 = enabled 1 5 - pll3 enable this bit controls whether the pll driving the lcd clock is enabled or not. rw 0 = disabled 1 = enabled 1 4- 0 3- cpu divider enable this bit controls whether the cpu output divider is enabled or not. note: this bit should be automatically set to ?0? if bit 7 is set to ?0?. rw 0 = disabled 1 = enabled 1 2- src output divider enable this bit controls whether the src output divider is enabled or not. note: this bit should be automatically set to ?0? if bit 7 is set to ?0?. rw 0 = disabled 1 = enabled 1 1- lcd output divider enable this bit controls whether the lcd output divider is enabled or not. note: this bit should be automatically set to ?0? if bit 5 is set to ?0?. rw 0 = disabled 1 = enabled 1 0- dot output divider enable this bit controls whether the dot output divider is enabled or not. note: this bit should be automatically set to ?0? if bit 6 is set to ?0?. rw 0 = disabled 1 = enabled 1 byte 1 pll ss enable/control register bit ( s ) pin # name descri p tion t yp e 0 1 default 7 pll1 ss enable this bit controls whether pll1 has spread enabled or not. spread spectrum for pll1 is set at -0.5% down-spread. note that pll1 drives the cpu and src clo cks. rw 0 = disabled 1 = enabled 1 6 pll3 ss enable this bit controls whether pll3 has spread enabled or not. note that pll3 drives the ssc clock, and that the spread spectrum amount is set in bits 3-5. rw 0 = disabled 1 = enabled 1 5 0 4 0 3 0 2 reserved 0 1 reserved 0 0 reserved 0 reserved see table 2: lcd spread select table pll3 fs select these 3 bits select the frequency of pll3 and the ssc clock when byte 1 bit 6 (pll3 spread spectrum enable) is set. rw
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 11 byte 2 output enable register bit ( s ) pin # name descri p tion t yp e 0 1 default 7 cpu0 enable this bit controls whether the cpu[0] output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 6 cpu1 enable this bit controls whether the cpu[1] output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 5 cpu2 enable this bit controls whether the cpu[2] output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 4 src0 enable this bit controls whether the src[0] output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 3 src1 enable this bit controls whether the src[1] output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 2 src2 enable this bit controls whether the src[2] output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 1 dot enable this bit controls whether the dot output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 0 lcd100 enable this bit controls whether the lcd output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 byte 3 output control register bit ( s ) pin # name descri p tion t yp e 0 1 default 7 reserved 0 6 reserved 0 5 ref enable this bit controls whether the ref output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 4 3 2 cpu0 stop enable this bit controls whether the cpu[0] output buffer is free-running or stoppable. if it is set to stoppable the cpu[0] output buffer w ill be disabled with the assertion of cpu_stp#. rw free running stoppable 0 1 cpu1 stop enable this bit controls whether the cpu[1] output buffer is free-running or stoppable. if it is set to stoppable the cpu[1] output buffer w ill be disabled with the assertion of cpu_stp#. rw free running stoppable 0 0 cpu2 stop enable this bit controls whether the cpu[2] output buffer is free-running or stoppable. if it is set to stoppable the cpu[2] output buffer w ill be disabled with the assertion of cpu_stp#. rw free running stoppable 0 10 00 = slow edge rate 01 = medium edge rate 10 = fast edge rate 11 = reserved rw these bits control the edge rate of the ref clock. ref slew
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 12 byte 4 cpu pll m/n register bit ( s ) pin # name control function t yp e 0 1 default bit 7 cpu n div8 n divider prog bit 8 rw x bit 6 cpu n div9 n divider pro g bit 9 rw x bit 5 cpu m div5 rw x bit 4 cpu m div4 rw x bit 3 cpu m div3 rw x bit 2 cpu m div2 rw x bit 1 cpu m div1 rw x bit 0 cpu m div0 rw x byte 5 cpu pll m/n register bit ( s ) pin # name control function t yp e 0 1 default bit 7 cpu n div7 rw x bit 6 cpu n div6 rw x bit 5 cpu n div5 rw x bit 4 cpu n div4 rw x bit 3 cpu n div3 rw x bit 2 cpu n div2 rw x bit 1 cpu n div1 rw x bit 0 cpu n div0 rw x byte 6 dot96 pll m/n register bit ( s ) pin # name control function t yp e 0 1 default bit 7 dot n div8 n divider pro g bit 8 rw x bit 6 dot n div9 n divider pro g bit 9 rw x bit 5 dot m div5 rw x bit 4 dot m div4 rw x bit 3 dot m div3 rw x bit 2 dot m div2 rw x bit 1 dot m div1 rw x bit 0 dot m div0 rw x byte 7 dot96 pll m/n register bit ( s ) pin # name control function t yp e 0 1 default bit 7 dot n div7 rw x bit 6 dot n div6 rw x bit 5 dot n div5 rw x bit 4 dot n div4 rw x bit 3 dot n div3 rw x bit 2 dot n div2 rw x bit 1 dot n div1 rw x bit 0 dot n div0 rw x the decimal representation of m and n divider in byte 4 and 5 w ill configure the cpu vco frequency. default at power up = latch-in. vco frequency = 14.318 x [ndiv(11:0)] / [mdiv(5:0)] m divider programming bit (5:0) m divider programming bit (5:0) the decimal representation of m and n divider in byte 6 and 7 w ill configure the dot vco frequency. vco frequency = 14.318 x [ndiv(11:0)] / [mdiv(5:0)] n divider programming byte7 bit(7:0) and byte6 bit(7:6) the decimal representation of m and n divider in byte 6 and 7 w ill configure the dot vco frequency. vco frequency = 14.318 x [ndiv(11:0)] / [mdiv(5:0)] n divider programming byte5 bit(7:0) and byte5 bit(7:6) the decimal representation of m and n divider in byte 4 and 5 w ill configure the cpu vco frequency. default at power up = latch-in. vco frequency = 14.318 x [ndiv(11:0)] / [mdiv(5:0)]
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 13 byte 8 lcd100 pll m/n register bit ( s ) pin # name control function t yp e 0 1 default bit 7 lcd100 n div8 n divider pro g bit 8 rw x bit 6 lcd100 n div9 n divider pro g bit 9 rw x bit 5 lcd100 m div5 rw x bit 4 lcd100 m div4 rw x bit 3 lcd100 m div3 rw x bit 2 lcd100 m div2 rw x bit 1 lcd100 m div1 rw x bit 0 lcd100 m div0 rw x byte 9 lcd100 pll m/n register bit ( s ) pin # name control function t yp e 0 1 default bit 7 lcd100 n div7 rw x bit 6 lcd100 n div6 rw x bit 5 lcd100 n div5 rw x bit 4 lcd100 n div4 rw x bit 3 lcd100 n div3 rw x bit 2 lcd100 n div2 rw x bit 1 lcd100 n div1 rw x bit 0 lcd100 n div0 rw x byte 10 status readback register bit ( s ) pin # name descri p tion t yp e 0 1 default 7 37 fsb frequency select b r latch 6 9 fsc frequency select c r latch 5 24 cr0# readbk real time cr0# state indicator r cr0# is lo w cr0# is hi g hx 4 28 cr1# readbk real time cr1# state indicator r cr1# is lo w cr1# is hi g hx 3 36 cr2# readbk real time cr2# state indicator r cr2# is low cr2# is high x 2 reserved 0 1 reserved 0 0 reserved 0 byte 11 revision id/vendor id register bit ( s ) pin # name descri p tion t yp e 0 1 default 7 rev code bit 3 r x 6 rev code bit 2 r x 5 rev code bit 1 r x 4 rev code bit 0 r x 3 vendor id bit 3 r 0 2 vendor id bit 2 r 0 1 vendor id bit 1 r 0 0 vendor id bit 0 r 1 the decimal representation of m and n divider in byte 8 and 9 w ill configure the dot vco frequency. vco frequency = 14.318 x [ndiv(11:0)] / [mdiv(5:0)] m divider programming bit (5:0) n divider programming byte9 bit(7:0) and byte8 bit(7:6) the decimal representation of m and n divider in byte 8 and 9 w ill configure the dot vco frequency. vco frequency = 14.318 x [ndiv(11:0)] / [mdiv(5:0)] vendor id vendor specific see table 1: cpu frequency select table revision id
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 14 byte 12 device id register bit ( s ) pin # name descri p tion t yp e 0 1 default 7 dev_id3 device id msb r 1 6 dev_id2 device id 2 r 0 5 dev_id1 device id 1 r 1 4 dev_id0 device id lsb r 0 3 reserved 0 2 reserved 0 1 reserved 0 0 reserved 0 byte 13 reserved register bit ( s ) pin # name control function t yp e 0 1 default bit 7 reserved 0 bit 6 reserved 0 bit 5 reserved 0 bit 4 reserved 0 bit 3 reserved 0 bit 2 reserved 0 bit 1 reserved 0 bit 0 reserved 0 byte 14 reserved register bit ( s ) pin # name control function t yp e 0 1 default bit 7 reserved 0 bit 6 reserved 0 bit 5 reserved 0 bit 4 reserved 0 bit 3 reserved 0 bit 2 reserved 0 bit 1 reserved 0 bit 0 reserved 0 byte 15 byte count register bit ( s ) pin # name control function t yp e 0 1 default bit 7 reserved 0 bit 6 bc6 byte count 6 (msb) rw 0 bit 5 bc5 byte count 5 rw 0 bit 4 bc4 byte count 4 rw 0 bit 3 bc3 byte count 3 rw 1 bit 2 bc2 byte count 2 rw 1 bit 1 bc1 byte count 1 rw 1 bit 0 bc0 byte count lsb rw 1 specifies number of bytes to be read back during an smbus read. default is 0xf.
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 15 byte 16 m/n enable register bit ( s ) pin # name control function t yp e 0 1 default bit 7 mn enable enables pll mn pro g rammin g rw mn disabled mn enabled 0 bit 6 reserved 0 bit 5 reserved 0 bit 4 reserved 0 bit 3 reserved 0 bit 2 reserved 0 bit 1 reserved 0 bit 0 reserved 0 byte 17 cpu pll spread spectrum index register bit ( s ) pin # name control function t yp e 0 1 default bit 7 cpussp7 rw x bit 6 cpussp6 rw x bit 5 cpussp5 rw x bit 4 cpussp4 rw x bit 3 cpussp3 rw x bit 2 cpussp2 rw x bit 1 cpussp1 rw x bit 0 cpussp0 rw x byte 18 cpu pll spread spectrum index register bit ( s ) pin # name control function t yp e 0 1 default bit 7 cpussp15 rw x bit 6 cpussp14 rw x bit 5 cpussp13 rw x bit 4 cpussp12 rw x bit 3 cpussp11 rw x bit 2 cpussp10 rw x bit 1 cpussp9 rw x bit 0 cpussp8 rw x byte 19 lcd100 pll spread spectrum index register bit ( s ) pin # name control function t yp e 0 1 default bit 7 lcdssp7 rw x bit 6 lcdssp6 rw x bit 5 lcdssp5 rw x bit 4 lcdssp4 rw x bit 3 lcdssp3 rw x bit 2 lcdssp2 rw x bit 1 lcdssp1 rw x bit 0 lcdssp0 rw x spread spectrum programming bit(7:0) contact idt before editing these values. these spread spectrum bits in byte 19 and 20 w ill program the spread percentage of the cpu and src outputs spread spectrum programming bit(7:0) contact idt before editing these values. these spread spectrum bits in byte 17 and 18 w ill program the spread percentage of the cpu and src outputs spread spectrum programming bit(15:8) contact idt before editing these values. these spread spectrum bits in byte 17 and 18 w ill program the spread percentage of the cpu and src outputs
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 16 byte 20 lcd100 pll spread spectrum index register bit ( s ) pin # name control function t yp e 0 1 default bit 7 lcdssp15 rw x bit 6 lcdssp14 rw x bit 5 lcdssp13 rw x bit 4 lcdssp12 rw x bit 3 lcdssp11 rw x bit 2 lcdssp10 rw x bit 1 lcdssp9 rw x bit 0 lcdssp8 rw x byte 21 cpu pll m/n register bit ( s ) pin # name control function t yp e 0 1 default bit 7 cpu ndiv 10 n divider prog bit 10 rw x bit 6 cpu ndiv 11 n divider pro g bit 11 rw x bit 5 reserved 0 bit 4 reserved 0 bit 3 reserved 0 bit 2 reserved 0 bit 1 reserved 0 bit 0 reserved 0 byte 22 lcd100 pll m/n register bit ( s ) pin # name control function t yp e 0 1 default bit 7 lcd ndiv 10 n divider prog bit 10 rw x bit 6 lcd ndiv 11 n divider pro g bit 11 rw x bit 5 reserved 0 bit 4 reserved 0 bit 3 reserved 0 bit 2 reserved 0 bit 1 reserved 0 bit 0 reserved 0 see byte 8/9 description see byte 4/5 description spread spectrum programming bit(15:8) contact idt before editing these values. these spread spectrum bits in byte 19 and 20 w ill program the spread percentage of the cpu and src outputs
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 17 test clarification table comments test_sel hw pin test_mode hw pin output <0.35v x normal >0.7v<0.35vhi-z >0.7v >0.7v ref/n h w power-up w/ test_sel = 1 to enter test mode cycle power to disable test mode test_mode -->low vth input test_mode is a real time input
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 18 mlf top mark information (9ums9610) line 1. company name line 2. part number line 3. yyww = date code line 3. country of origin line 4. ####### = lot number 48 47 46 45 44 43 42 41 40 39 38 37 136 235 334 433 532 631 730 829 928 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 ics ums9610yl yyww c of o #######
idt tm /icst m pc main clock 1336?06/01/09 ICS9UMS9610 pc main clock 19 ordering information dimensions a0.81.0 n 48 a1 0 0.05 n d 12 a3 n e 12 b 0.18 0.3 d x e basic 6.00 x 6.00 e d2 min. / max. 3.95 / 4.25 e2 min. / max. 3.95 / 4.25 l min. / max. 0.30 / 0.50 0.20 reference 0.40 basic 48l tolerance thermally enhanced, very thin, fine pitch quad flat / no lead plastic package dimensions symbol min. max. symbol top view index area d sawn singulation anvil singulation a 0. 08 c c a3 a1 seating plane e2 e2 2 l (n -1)x e (ref.) & n n even n e d2 2 d2 (re f.) & odd 1 2 e 2 (typ.) (ref.) (ref.) if n & n (n -1)x b thermal base n or chamfer 4x 0.6 x 0.6 max optional e d n n d d d are even part / order number marking shipping packaging package temperature 9ums9610cklf tubes 48-pin mlf 0 to +85 c 9ums9610cklft tape and reel 48-pin mlf 0 to +85 c parts that are ordered w ith a "lf" suffix to the part num ber are the pb-free configuration and are rohs com pliant. see page 18
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm ICS9UMS9610 pc main clock 20 revision history rev. issue date description page # 0.1 04/25/07 initial release - 0.15 05/03/07 corrected clkpwrgd#/pd polarity 1 0.2 5/18/2007 updated test clarification table with the correct voltage levels. - 0.3 8/31/2007 updated input pin names to indicate maximum input volta g e level - 0.4 9/11/2007 added logic level and input level tolerance columns to pin descriptions. 2, 3 0.5 9/13/2007 clarified that x1 is 1.5v only input 2 0.6 10/23/007 1. byte count in byte 15 is 7 bits, not 8 bits. b15b7 is now reserved. 2. modified pll programming formulas in bytes(4:9). n is 12 bits instead of 10 bits. 3. changed ref_3.3 output name to reflect default drive strength (new name is ref_3.3_2x). various 0.7 11/6/2007 updated b y tes [9:4]. 12-13 0.8 11/29/2007 added bytes 16-22 to the smbus. 15-16 0.9 2/26/2008 added mlf top mark information. 18 0.91 7/8/2008 updated electrical specifications 5-7 0.92 7/21/2008 updated electrical specifications 5-7 a 5/21/2009 moved to final. - b 6/1/2009 updated electrical specs; ta spec in ordering information. various

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